This invention relates generally to computer memories. In particular, the invention is related to hierarchical memory systems.
Almost all computer systems include some type of memory. The predominant type of memory used for computer application is random access memory (RAM) although larger systems requiring vast amounts of memory storage typically include additional serial memory, usually in the form of magnetic tapes or discs. In simpler computer systems, the one or more memories are directly connected to the processor which then directly reads into and writes from a selected memory device.
However, there is a trend toward hierarchical memories in which a larger, higher level memory is not connected directly to the processor but instead transmits to and receives data from a lower level memory. The lower level memory receives data from and transmits data to, not only the higher level memory, but also the computer. A cache memory is one example of a lower level memory. The concept of multi-level memories may be extended to more than two levels of memory.
An example of a hierarchical memory is illustrated in FIG. 1, in which two memory cards 10 and 12 contain respectively a low level memory and a high level memory. Each card 10 or 12 contains an array of memory chips 14 and 16. Typically, the memory chips of the low level memory 10 are faster but of fewer number than the memory chips 16 of the high level memory 12. Thus the high level memory 12 is used for bulk storage while the low level memory 10 is used for its fast access and buffering capability. The low level memory 10 provides data from its memory chips 14 to the computer systems through a primary port 18 and a fast data channel 20. Similary, the low level memory provides data to the high level memory 12 through a secondary port 21 which is connected to an I/O port 22 of the high level memory 12. The secondary port 21 and the I/O port 22 are connected by an inter-level channel 24. Data transmission on the two channels 20 and 24 can be done in either direction. In typical designs, the low level memory 10 can operate only one of its ports 18 and 21 at any one time. That is, the low level memory 10 either selects the primary port 18 for access by the data channel 20 to the computer system or alternatively selects the secondary port 21 for access by the inter-level channel 24 and the high level memory 12. The data channel 20 usually is a high speed channel, matched to the computer system, and is a parallel bus. In contrast, the inter-level channel 24 has a different channel capacity. The low level memory 10 provides buffering between the differing data rates on the two channels 20 and 24.
A disadvantage of the memory system of FIG. 1 is the lack of simultaneous access of the two ports 18 and 21 to the memory chips 14. While data is being accessed through the secondary port 21, either in a read or a write mode the memory chips 14 cannot be accessed by the data channel 20, thus impacting the operation of the fast paced computer system. Another disadvantage is that during the serial accesses through the secondary port 21, the memory chips 14 and their support circuitry need to be fully powered at a power level dictated by the inherent cycle time of the chip. As a result, the memory system of FIG. 1 is slow and also demands full power for each access.
Two patent applications, commonly assigned to the assignee of this application, disclose the use of dual ported memory chips in a hierarchical memory system. These applications are Ser. No. 405,812 filed Aug. 6, 1982 by Lavalee et al. (now U.S. Pat. No. 4,489,381) and Ser. No. 626,564 filed June 29, 1984 by Aichelmann et al.